Active circuit for synthesizing an inductor

ABSTRACT

A circuit for an apparatus is an active circuit that synthesizes self-induction. The active circuit comprises only one operational amplifier. With the use of tunable capacitors, the inductor synthesized by the active circuit becomes a tunable inductor.

FIELD OF THE INVENTION

The present invention is related to active circuits, in particularactive inductors, which are incorporated in integrated circuits.

STATE OF THE ART

Active inductors have been described, for example in document U.S. Pat.No. 6,028,496, which is related to a device comprising two OperationalAmplifiers (OPAMPS). The active inductor of this document includes aninverting amplifier of a common source (common emitter) type, whichinversely amplifies an input signal and outputs the amplified signal asan output signal, a non-inverting amplifier of a common gate (commonbase) type, which non-inversely amplifies the output signal and theamplified signal as the input signal, a capacitor connected between theinput signal and a reference signal, and a biasing portion for biasingthe inverting amplifier and the non-inverting amplifier.

A general drawback of these existing active inductors is the fact thatthey all comprise at least two Operational Amplifiers, leading to arelatively high power consumption.

AIMS OF THE INVENTION

The present invention aims to provide an active inductor which consumesless power compared to the active inductors belonging to the currentstate of the art.

SUMMARY OF THE INVENTION

The present invention is related to an apparatus comprising an activecircuit, the circuit synthesising an inductor, characterised in that thecircuit comprises one Operational Amplifier.

According to a preferred embodiment, the invention is related to anapparatus comprising an active circuit, wherein the circuit comprises:

an Operational Amplifier with a non-inverting input terminal, aninverting input terminal, a non-inverting output terminal and aninverting output terminal,

a first resistor R1 and a first capacitance C1, connected in cascadebetween the inverting input terminal and a first output terminal of theactive circuit,

a second resistor R1′, having the same resistance as R1, and a secondcapacitance C1′, having the same capacitance value as C1, connected incascade between the non-inverting input terminal and a second outputterminal of said the active circuit,

a third resistor R2 and a fourth resistor R3, connected in cascadebetween the non-inverting input terminal and the first output terminalof the circuit,

a fifth resistor R2′, having the same resistance as R2, and a sixthresistor R3′, having the same resistance as R3, the resistors R2′ andR3′ being connected in cascade between the inverting input terminal andthe second output terminal of the circuit,

a seventh resistor Rx and a third capacitance Cx, connected in parallel,and coupled between the inverting output terminal and a common node ofthe third resistor R2 and the fourth resistor R3,

an eighth resistor Rx′, having the same resistance as Rx, and a fourthcapacitance Cx′, having the same capacitance value as Cx, the resistorRx′ and the capacitance Cx′ being connected in parallel, and coupledbetween the non-inverting output terminal and a common node of the fifthresistor R2′ and the sixth resistor R3 ′,

a ninth resistor R4 connected between the inverting output terminal andthe first output terminal of the circuit, and an tenth resistor R4′,connected between the non-inverting output terminal and the secondoutput terminal of said circuit.

According to the preferred embodiment of the present invention, theresistance values of R4 and R4′ obey the following formula:${R4} = {{R4}^{\prime} = \frac{{\left( {{{C1} \cdot {R1}} + {\left( {{2{C1}} - {Cx}} \right) \cdot {Rx}}} \right) \cdot {R3}} + {{C1} \cdot {R1} \cdot {Rx}}}{{{Cx} \cdot {Rx}} - {{C1} \cdot {R1}}}}$

According to a further embodiment, the invention is related to anapparatus wherein the inductor synthesised by said active circuit istuneable. This may be realised by making the capacitors C1, C1′, Cx andCx′ tuneable.

According to another embodiment, the ratio between C1 and Cx isconstant.

According to another embodiment, the value Rx.Cx is greater than R1.C1.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 represents the circuit of an active inductor according to thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 1, the device according to a preferred embodiment ofthe invention is hereafter disclosed. The main characteristic of theinvention is the fact that an active circuit is proposed, forsynthesising an inductor, comprising only one Operational Amplifier.

The circuit can be made tuneable in order to select the self-inductancevalue. FIG. 1 shows the embodiment wherein the circuit is tuneable, dueto the presence of tuneable capacitors. An alternative would be the useof tuneable resistors or a combination of tuneable resistors andcapacitors.

The operational amplifier 1 has non-inverting and inverting inputterminals 2 and 3, and non-inverting and inverting output terminals 4and 5.

The inverting input terminal 3 of the operational amplifier 1 is coupledvia the cascade connection of a resistor R1 and a tuneable capacitanceC1 to a first output terminal 6 of the circuit, and is coupled via thecascade connection of two resistors R2′ and R3′ to a second outputterminal 7 of the circuit.

The non-inverting input terminal 2 of the operational amplifier 1 iscoupled via the cascade connection of a resistor R1′ and a tuneablecapacitance C1′ to the second output terminal 7 of the circuit, and iscoupled via the cascade connection of two resistors R2 and R3 to thefirst output terminal 6 of the circuit.

The inverting output terminal 5 of the operational amplifier 1 iscoupled via a resistor R4 to the first output terminal 6 of the circuit,and via the parallel connection of an tuneable capacitance Cx and aresistor Rx to the common node of the resistors R2 and R3.

The non-inverting output terminal 4 of the operational amplifier 1 iscoupled via a resistor R4′ to the second output terminal 7 of thecircuit, and via the parallel connection of a tuneable capacitance Cx′and a resistor Rx′ to the common node of the resistors R2′ and R3′.

In the following discussion, taken with reference to the drawing FIGURE,it will be appreciated that +V_(A) and −V_(A) in the FIGURE representthe voltage at terminals 6 and 7, respectively, that +V_(B) is thevoltage at the otherwise unlabeled node by which the symbol +V_(B)appears (this voltage may also be referred to simply as V_(B)), and that+V_(C) is the voltage at the otherwise unlabeled node by which thesymbol +V_(C) appears (this voltage may also be referred to simply asV_(C)).

The following is true for the values of the above described resistorsand capacitances:

R1=R1′; R2=R2′; R3=R3′; R4=R4′; Rx=Rx′; C1=C1′; Cx=Cx′

According to the invention, the resistor R₄ (and R4′) is chosen suchthat:$R_{4} = {R_{4}^{\prime} = \frac{{\left( {{C_{1} \cdot R_{1}} + {\left( {{2C_{1}} - C_{X}} \right) \cdot R_{X}}} \right) \cdot R_{3}} + {C_{1} \cdot R_{1} \cdot R_{X}}}{{C_{X} \cdot R_{X}} - {C_{1} \cdot R_{1}}}}$

As a result, the synthesised impedance behaves like the serialconnection of a resistor and an inductor:

Z _(SYNTH) =R _(SYNTH) +jωL _(SYNTH).

Herein:$R_{SYNTH} = {\frac{2 \cdot R_{3} \cdot R_{4}}{R_{3} + R_{4} + R_{X}}\quad {and}}$$L_{SYNTH} = {\frac{2 \cdot R_{3} \cdot R_{4} \cdot R_{X} \cdot C_{X}}{R_{3} + R_{4} + R_{X}} = {R_{SYNTH} \cdot R_{X} \cdot {C_{X}.}}}$

This is proven by the following mathematical derivation. The synthesizedimpedance is given by: $\begin{matrix}{Z_{SYNTH} = {\frac{V_{A} - \left( {- V_{A}} \right)}{I} = \frac{2V_{A}}{I}}} & (1)\end{matrix}$

with V_(A) being the supply voltage.

The current 1 shown in FIG. 1, can be written as a function of currentsI₁, I₃, and I₄:

I=I ₁ +I ₃ +I ₄  (2)

I₁, I₃, and I₄ are determined below.

I₁ can be determined by expressing that the operational amplifier 1 isvirtually grounded: $\begin{matrix}{I_{1} = {\frac{V_{A} - 0}{Z_{1}} = \frac{V_{A}}{Z_{1}}}} & (3) \\{{Herein},\quad {Z_{1} = {R_{1} + \frac{1}{{j\omega}\quad C_{1}}}}} & (4) \\{{Furthermore},\quad {I_{3} = {\frac{V_{A} - V_{B}}{R_{3}}\quad {with}}}} & (5) \\{V_{B} = {R_{2} \cdot I_{2}}} & (6)\end{matrix}$

Kirchoff's law applied at the non-inverting input 2 results in:$\begin{matrix}{{{- I_{1}} + I_{2}} = {\left. 0\Rightarrow I_{2} \right. = {I_{1} = \frac{V_{A}}{Z_{1}}}}} & (7)\end{matrix}$

Substituting (7) in (6) results in: $\begin{matrix}{V_{B} = {V_{A} \cdot \frac{R_{2}}{Z_{1}}}} & (8)\end{matrix}$

so that (5) turns into: $\begin{matrix}{I_{3} = {{V_{A} \cdot \frac{1 - \frac{R_{2}}{Z_{1}}}{R_{3}}} = {V_{A} \cdot \frac{Z_{1} - R_{2}}{R_{3} \cdot Z_{1}}}}} & (9)\end{matrix}$

From FIG. 1, one derives that: $\begin{matrix}{I_{4} = {\frac{V_{A} - V_{C}}{R_{4}}\quad {with}}} & (10) \\{V_{C} = {V_{B} + {I_{X} \cdot Z_{X}}}} & (11) \\{{Herein},\quad {Z_{X} = {{R_{X}//C_{X}} = {\frac{1}{\frac{1}{R_{X}} + {{j\omega}\quad C_{X}}} = \frac{R_{X}}{1 + {{j\omega}\quad {R_{X} \cdot C_{X}}}}}}}} & (12)\end{matrix}$

Kirchoff's law applied in the VB node, results in:

I ₃ +I _(x) −I ₂=0→I _(x) =I ₂ −I ₃  (b 13)

After substitution of (7) and (9) in (13), one obtains: $\begin{matrix}{I_{X} = {{\frac{V_{A}}{Z_{1}} - {V_{A} \cdot \frac{Z_{1} - R_{2}}{R_{3} \cdot Z_{1}}}} = {V_{A} \cdot \frac{R_{2} + R_{3} - Z_{1}}{R_{3} \cdot Z_{1}}}}} & (14)\end{matrix}$

From equation (11), V_(C) can now be derived: $\begin{matrix}{\begin{matrix}{V_{C} = {{V_{A} \cdot \frac{R_{2}}{Z_{1}}} + {V_{A} \cdot \frac{Z_{X} \cdot \left( {R_{2} + R_{3} - Z_{1}} \right)}{R_{3} \cdot Z_{1}}}}} \\{= {V_{A} \cdot \frac{{R_{3} \cdot R_{2}} + {Z_{X} \cdot \left( {R_{2} + R_{3} - Z_{1}} \right)}}{R_{3} \cdot R_{4} \cdot Z_{1}}}}\end{matrix}} & (15)\end{matrix}$

(15) can be substituted in equation (10), resulting in: $\begin{matrix}{I_{4} = {V_{A} \cdot \frac{{R_{3} \cdot Z_{1}} - {R_{3} \cdot R_{2}} + {Z_{X} \cdot \left( {Z_{1} - R_{2} - R_{3}} \right)}}{R_{3} \cdot R_{4} \cdot Z_{1}}}} & (16)\end{matrix}$

The expressions found in (3), (9) and (16) are to be substituted in (2)to find the current I: $\begin{matrix}\begin{matrix}{I = {I_{1} + I_{3} + I}} \\{= {V_{A} \cdot \frac{\begin{matrix}{{R_{3} \cdot R_{4}} - {R_{2} \cdot R_{4}} + {Z_{1} \cdot R_{4}} + {R_{3} \cdot Z_{1}} -} \\{{R_{3} \cdot R_{2}} + {Z_{X} \cdot \left( {Z_{1} - R_{2} - R_{3}} \right)}}\end{matrix}}{R_{3} \cdot R_{4} \cdot Z_{1}}}} \\{= {V_{A} \cdot \frac{\begin{matrix}{{\left( {R_{3} + R_{4}} \right) \cdot \left( {Z_{1} - R_{2}} \right)} + {\frac{R_{3} \cdot R_{4}}{R_{3} + R_{4}} \cdot}} \\{\left( {R_{3} + R_{4}} \right) + {Z_{X} \cdot \left( {Z_{1} - R_{2} - R_{3}} \right)}}\end{matrix}}{R_{3} \cdot R_{4} \cdot Z_{1}}}}\end{matrix} & (17) \\{{Herein},\quad {\frac{R_{3} \cdot R_{4}}{R_{3} + R_{4}} = {R_{3}//R_{4}}}} & (18)\end{matrix}$

and consequently: $\begin{matrix}{I = {V_{A} \cdot \frac{{\left( {R_{3} + R_{4}} \right) \cdot \left( {{Z_{1} - R_{2} + R_{3}}//R_{4}} \right)} + {Z_{X} \cdot \left( {Z_{1} - R_{2} - R_{3}} \right)}}{R_{3} \cdot R_{4} \cdot Z_{1}}}} & (19)\end{matrix}$

R₂ is chosen as specified by (20)

R ₂ =R ₁ +R ₃ //R ₄ ≈R ₁ +R ₃  (20)

In order to fulfill the approximate equality, R₃ should preferably notbe higher than 20% of R₄.

and by substituting (4) and (12) in (19), the expression for I becomes:$\begin{matrix}{I = {\frac{\begin{matrix}{\left( {R_{3} + R_{4} + R_{X}} \right) \cdot} \\\left( {1 + {{j\omega}\quad \frac{{C_{X} \cdot R_{X} \cdot \left( {R_{3} + R_{4}} \right)} - {2 \cdot C_{1} \cdot R_{3} \cdot R_{X}}}{R_{3} + R_{4} + R_{X}}}} \right)\end{matrix}}{{R_{3} \cdot R_{4} \cdot \left( {1 + {{j\omega C}_{1} \cdot R_{1}}} \right)}1\left( {1 + {{j\omega}\quad {R_{X} \cdot C_{X}}}} \right)} \cdot V_{A}}} & (21)\end{matrix}$

If R₄ is now chosen such that: $\begin{matrix}{R_{4} = \frac{{\left( {{C_{1} \cdot R_{1}} + {\left( {{2C_{1}} - C_{X}} \right) \cdot R_{X}}} \right) \cdot R_{3}} + {C_{1} \cdot R_{1} \cdot R_{X}}}{{C_{X} \cdot R_{X}} - {C_{1} \cdot R_{1}}}} & (22)\end{matrix}$

and (21) is substituted into (1), then the synthesized impedance behaveslike the serial connection of a resistor and an inductor:

Z _(SYNTH) =R _(SYNTH) +jωL _(SYNTH)  (23)

with $\begin{matrix}{R_{S\quad Y\quad N\quad T\quad H} = {\frac{2 \cdot R_{3} \cdot R_{4}}{R_{3} + R_{4} + R_{X}}\quad {and}}} & (24) \\{L_{S\quad Y\quad N\quad T\quad H} = {\frac{2 \cdot R_{3} \cdot R_{4} \cdot R_{X} \cdot C_{X}}{R_{3} + R_{4} + R_{X}} = {R_{S\quad Y\quad N\quad T\quad H} \cdot R_{X} \cdot C_{X}}}} & (25)\end{matrix}$

The resistor R_(SYNTH) can be made smaller than 1 Ω by choosing a highRx, while the inductor can be a few μH. In order to keep R4 constantwith C1 and Cx variable, a constant ratio should be chosen between C1and Cx. Typically, Rx.Cx must be greater than R1.C1 in order to have asignificantly high inductance with a small resistor value.

For example:

R1=R1′=500 ω

R3=R3′=10 ω

R2=R2′32 510 ω

Rx=Rx′=1500 ω

R4=R4′=82 ω

RSYNTH=1.1 ω

Cx/C1=6

For LSYNTH=2 μH, we find Cx=1.21 nF

What is claimed is:
 1. A circuit for synthesizing an inductor,comprising: an operational amplifier with a non-inverting inputterminal, an inverting input terminal, a non-inverting output terminaland an inverting output terminal; a first resistor R1 and a firstcapacitance C1, connected in cascade between said inverting inputterminal and a first output terminal of said active circuit; a secondresistor R1′, having the same resistance as R1, and a second capacitanceC1′, having the same capacitance value as C1, connected in cascadebetween said non-inverting input terminal and a second output terminalof said active circuit; a third resistor R2 and a fourth resistor R3,connected in cascade between said non-inverting input terminal and saidfirst output terminal of said circuit; a fifth resistor R2′, having thesame resistance as R2, and a sixth resistor R3′, having the sameresistance as R3, said resistors R2′ and R3′ being connected in cascadebetween said inverting input terminal and said second output terminal ofsaid circuit; a seventh resistor Rx and a third capacitance Cx,connected in parallel, and coupled between said inverting outputterminal and a common node of said third resistor R2 and said fourthresistor R3; an eighth resistor Rx′, having the same resistance as Rx,and a fourth capacitance Cx′, having the same capacitance value as Cx,said resistor Rx′ and said capacitance Cx′ being connected in parallel,and coupled between said non-inverting output terminal and a common nodeof said fifth resistor R2′ and said sixth resistor R3′; and a ninthresistor R4 connected between said inverting output terminal and saidfirst output terminal of said circuit, and an tenth resistor R4′,connected between said non-inverting output terminal and said secondoutput terminal of said circuit.
 2. The circuit according to claim 1,wherein the value Rx.Cx is greater than R1.C1.
 3. The circuit accordingto claim 1, wherein${R4} = {{R4}^{\prime} = {\frac{{\left( {{{C1} \cdot {R1}} + {{\left( {{2{C1}} - {C\quad x}} \right) \cdot R}\quad x}} \right) \cdot {R3}} + {{{C1} \cdot {R1} \cdot R}\quad x}}{{C\quad {x \cdot R}\quad x} - {{C1} \cdot {R1}}}.}}$


4. The circuit according to claim 1, wherein the inductor synthesised bysaid active circuit is tunable.
 5. The circuit according to claim 4,wherein said capacitors C1, C1′, Cx and Cx′ are tunable.
 6. The circuitaccording to claim 1 wherein the ratio between C1 and Cx is constant.